[DistroKit] [PATCH 0/6] RFC: add support for imx8mp-frdm board

[DistroKit] [PATCH 0/6] RFC: add support for imx8mp-frdm board

[Fabian Pfitzner]

Add support for the imx8mp-frdm board. This patch assumes that Barebox
already offers board support, which is not the case yet. See [1].
Wait for it to be merged.

Furthermore, the kernel device-tree is not yet upstream [2].
Wait for it to be merged.

This patch stack imports it and additionally adds more features to it.

The board offers an IW612 WiFi chip, which requires an extra firmware
provided by the imx-firmware repository. I already sent a patch upstream
that integrates this as a package [3]. Wait for it to be merged.

Besides the firmware, the WiFi chip also needs the mwifiex driver. This
driver is already contained in the upstream Linux kernel, but does
not support the IW612 chip yet. Instead of backporting downstream driver
changes, that add support for this chip, I decided to wait for upstream
support. Otherwise, we would have several downstream patches in
DistroKit.

[1] https://lore.barebox.org/barebox/20260119-fpf-imx8mp-frdm-v1-0-13fac69eda23@pengutronix.de/T/#t
[2] https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/commit/?h=imx/dt64&id=bb5b318f11e6f41c8cbb51848555f58b9ef175e6
[3] https://lore.distrokit.org/distrokit/20260120085919.3684175-2-f.pfitzner@pengutronix.de/T/#u

Signed-off-by: Fabian Pfitzner <f.pfitzner@pengutronix.de>
---
Fabian Pfitzner (6):
      v8a: add imx8mp-frdm image
      v8a: enable imx8mp-frdm image
      v8a: barebox: enable imx8mp-frdm board
      v8a: kernel: add imx8mp-frdm dts
      v8a: kernel: import imx8mp-frdm device tree
      doc: add imx8mp-frdm

 configs/platform-v8a/barebox.config                |   4 +
 ...ts-add-support-for-NXP-i.MX8MP-FRDM-board.patch | 409 +++++++++++++++
 ...dts-imx8mp-frdm-import-downstream-changes.patch | 580 +++++++++++++++++++++
 configs/platform-v8a/patches/linux-6.18/series     |   5 +
 configs/platform-v8a/platformconfig                |   3 +-
 .../platform-v8a/platforms/image-imx8mp-frdm.in    |  10 +
 configs/platform-v8a/rules/image-imx8mp-frdm.make  |  35 ++
 doc/hardware_v8a_imx8mp_frdm.rst                   |  46 ++
 8 files changed, 1091 insertions(+), 1 deletion(-)
---
base-commit: 5efb124c6eecc8b70ced77a22fb14084311afb8f
change-id: 20260120-fpf-imx8mp-frdm-e0a34fe63a6a

Best regards,
-- 
Fabian Pfitzner <f.pfitzner@pengutronix.de>

[DistroKit] [PATCH 1/6] v8a: add imx8mp-frdm image

[Fabian Pfitzner]

Signed-off-by: Fabian Pfitzner <f.pfitzner@pengutronix.de>
---
 .../platform-v8a/platforms/image-imx8mp-frdm.in    | 10 +++++++
 configs/platform-v8a/rules/image-imx8mp-frdm.make  | 35 ++++++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/configs/platform-v8a/platforms/image-imx8mp-frdm.in b/configs/platform-v8a/platforms/image-imx8mp-frdm.in
new file mode 100644
index 0000000000000000000000000000000000000000..851eebee55c1769f4fcc08ac7d8348c09263484f
--- /dev/null
+++ b/configs/platform-v8a/platforms/image-imx8mp-frdm.in
@@ -0,0 +1,10 @@
+## SECTION=image
+
+config IMAGE_IMX8MP_FRDM
+	tristate
+	select HOST_GENIMAGE
+	select IMAGE_ROOT_EXT
+	select BAREBOX
+	prompt "Generate images/imx8mp-frdm.img"
+	help
+	  Generate a bootable SD card image to deploy a NXP i.MX8MP-FRDM board.
diff --git a/configs/platform-v8a/rules/image-imx8mp-frdm.make b/configs/platform-v8a/rules/image-imx8mp-frdm.make
new file mode 100644
index 0000000000000000000000000000000000000000..e602d59eae68b67f36c78e22a67059a7df3b252b
--- /dev/null
+++ b/configs/platform-v8a/rules/image-imx8mp-frdm.make
@@ -0,0 +1,35 @@
+# -*-makefile-*-
+#
+# Copyright (C) 2025 by Fabian Pfitzner <f.pfitzner@pengutronix.de>
+#
+# For further information about the PTXdist project and license conditions
+# see the README file.
+#
+
+#
+# We provide this package
+#
+IMAGE_PACKAGES-$(PTXCONF_IMAGE_IMX8MP_FRDM) += image-imx8mp-frdm
+
+#
+# Paths and names
+#
+IMAGE_IMX8MP_FRDM		:= image-imx8mp-fdrm
+IMAGE_IMX8MP_FRDM_DIR	:= $(BUILDDIR)/$(IMAGE_IMX8MP_FRDM)
+IMAGE_IMX8MP_FRDM_IMAGE	:= $(IMAGEDIR)/imx8mp-frdm.img
+IMAGE_IMX8MP_FRDM_FILES	:= $(IMAGEDIR)/root.tgz
+IMAGE_IMX8MP_FRDM_CONFIG	:= imx8m.config
+
+# ----------------------------------------------------------------------------
+# Image
+# ----------------------------------------------------------------------------
+
+IMAGE_IMX8MP_FRDM_ENV := \
+        BAREBOX_IMAGE=barebox-nxp-imx8mp-frdm.img
+
+$(IMAGE_IMX8MP_FRDM_IMAGE):
+	@$(call targetinfo)
+	@$(call image/genimage, IMAGE_IMX8MP_FRDM)
+	@$(call finish)
+
+# vim: syntax=make

-- 
2.47.3

[DistroKit] [PATCH 2/6] v8a: enable imx8mp-frdm image

[Fabian Pfitzner]

Signed-off-by: Fabian Pfitzner <f.pfitzner@pengutronix.de>
---
 configs/platform-v8a/platformconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/platform-v8a/platformconfig b/configs/platform-v8a/platformconfig
index 8c01dd19609a21b10f48acdeefdc3393012957f7..341a38ced51e17b779a810487e44552709581a61 100644
--- a/configs/platform-v8a/platformconfig
+++ b/configs/platform-v8a/platformconfig
@@ -251,6 +251,7 @@ PTXCONF_IMAGE_FIP_K3=y
 PTXCONF_IMAGE_IMX8MM_EVK=y
 PTXCONF_IMAGE_IMX8MN_EVK=y
 PTXCONF_IMAGE_IMX8MP_EVK=y
+PTXCONF_IMAGE_IMX8MP_FRDM=y
 PTXCONF_IMAGE_IMX8MQ_EVK=y
 PTXCONF_IMAGE_KERNEL=y
 

-- 
2.47.3

[DistroKit] [PATCH 3/6] v8a: barebox: enable imx8mp-frdm board

[Fabian Pfitzner]

Signed-off-by: Fabian Pfitzner <f.pfitzner@pengutronix.de>
---
 configs/platform-v8a/barebox.config | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/configs/platform-v8a/barebox.config b/configs/platform-v8a/barebox.config
index 4cb176f702dd02149d84f562673c2a6718a6b4b1..e70635a5e7cfa6b0c0d9df85ba2701bb4eccadd9 100644
--- a/configs/platform-v8a/barebox.config
+++ b/configs/platform-v8a/barebox.config
@@ -64,6 +64,7 @@ CONFIG_MACH_NXP_IMX8MM_EVK=y
 CONFIG_MACH_NXP_IMX8MN_EVK=y
 CONFIG_MACH_NXP_IMX8MP_EVK=y
 CONFIG_MACH_NXP_IMX8MQ_EVK=y
+CONFIG_MACH_NXP_IMX8MP_FRDM=y
 # CONFIG_MACH_PHYTEC_SOM_IMX8MM is not set
 CONFIG_MACH_PHYTEC_SOM_IMX8MQ=y
 # CONFIG_MACH_POLYHEX_DEBIX is not set
@@ -806,6 +807,7 @@ CONFIG_USB_DWC3=y
 # CONFIG_USB_DWC3_GADGET is not set
 CONFIG_USB_DWC3_DUAL_ROLE=y
 CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_DWC3_IMX8MP=y
 CONFIG_USB_DWC3_AM62=y
 CONFIG_USB_EHCI=y
 CONFIG_USB_XHCI=y
@@ -996,6 +998,7 @@ CONFIG_GPIO_ROCKCHIP=y
 # Pin controllers
 #
 CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_STATE_PARAM is not set
 CONFIG_PINCTRL_IMX_IOMUX_V3=y
 CONFIG_PINCTRL_ROCKCHIP=y
 CONFIG_PINCTRL_SINGLE=y
@@ -1086,6 +1089,7 @@ CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_GENERIC_PHY=y
 CONFIG_USB_NOP_XCEIV=y
 CONFIG_PHY_FSL_IMX8MQ_USB=y
+# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
 # CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set

-- 
2.47.3

[DistroKit] [PATCH 4/6] v8a: kernel: add imx8mp-frdm dts

[Fabian Pfitzner]

Signed-off-by: Fabian Pfitzner <f.pfitzner@pengutronix.de>
---
 configs/platform-v8a/platformconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/platform-v8a/platformconfig b/configs/platform-v8a/platformconfig
index 341a38ced51e17b779a810487e44552709581a61..c12104f9bc3babbdcf41af6c686f69669b317deb 100644
--- a/configs/platform-v8a/platformconfig
+++ b/configs/platform-v8a/platformconfig
@@ -137,7 +137,7 @@ PTXCONF_KERNEL_IMAGE_RAW=y
 PTXCONF_KERNEL_IMAGE="Image"
 PTXCONF_KERNEL_DTB=y
 PTXCONF_KERNEL_DTS_PATH="${PTXDIST_PLATFORMCONFIG_SUBDIR}/dts:${KERNEL_DIR}/arch/${GENERIC_KERNEL_ARCH}/boot/dts"
-PTXCONF_KERNEL_DTS="armada-3720-community.dts freescale/imx8mm-evk.dts freescale/imx8mn-ddr4-evk.dts freescale/imx8mp-evk.dts freescale/imx8mq-evk.dts rockchip/rk3568-rock-3a.dts freescale/imx8mp-tqma8mpql-mba8mpxl.dts freescale/imx93-tqma9352-mba93xxca.dts ti/k3-am625-beagleplay.dts imx93-11x11-frdm.dts"
+PTXCONF_KERNEL_DTS="armada-3720-community.dts freescale/imx8mm-evk.dts freescale/imx8mn-ddr4-evk.dts freescale/imx8mp-evk.dts freescale/imx8mq-evk.dts rockchip/rk3568-rock-3a.dts freescale/imx8mp-tqma8mpql-mba8mpxl.dts freescale/imx93-tqma9352-mba93xxca.dts ti/k3-am625-beagleplay.dts imx93-11x11-frdm.dts freescale/imx8mp-frdm.dts"
 # PTXCONF_KERNEL_DTBO is not set
 # PTXCONF_KERNEL_CODE_SIGNING is not set
 # PTXCONF_KERNEL_ZSTD is not set

-- 
2.47.3

[DistroKit] [PATCH 5/6] v8a: kernel: import imx8mp-frdm device tree

[Fabian Pfitzner]

As the imx8mp-frdm device tree is not yet upstream in the Linux kernel,
import it here [1]. Furthermore add downstream changes from NXP [2] that add
functionality for

- WiFi
- HDMI
- Ethernet
- USB
- SD Card

[1] https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/commit/?h=imx/dt64&id=bb5b318f11e6f41c8cbb51848555f58b9ef175e6
[2] git@github.com:nxp-imx/linux-imx.git

Signed-off-by: Fabian Pfitzner <f.pfitzner@pengutronix.de>
---
 ...ts-add-support-for-NXP-i.MX8MP-FRDM-board.patch | 409 +++++++++++++++
 ...dts-imx8mp-frdm-import-downstream-changes.patch | 580 +++++++++++++++++++++
 configs/platform-v8a/patches/linux-6.18/series     |   5 +
 3 files changed, 994 insertions(+)

diff --git a/configs/platform-v8a/patches/linux-6.18/0001-arm64-dts-add-support-for-NXP-i.MX8MP-FRDM-board.patch b/configs/platform-v8a/patches/linux-6.18/0001-arm64-dts-add-support-for-NXP-i.MX8MP-FRDM-board.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2607856b3bf5f14cbee854a2b667bf3b1c7cc281
--- /dev/null
+++ b/configs/platform-v8a/patches/linux-6.18/0001-arm64-dts-add-support-for-NXP-i.MX8MP-FRDM-board.patch
@@ -0,0 +1,409 @@
+From: Rogerio Pimentel <rpimentel.silva@gmail.com>
+Date: Sun, 23 Nov 2025 13:14:44 -0500
+Subject: [PATCH] arm64: dts: add support for NXP i.MX8MP FRDM board
+
+The FRDM-i.MX8MP is an NXP development platform based on the i.MX8M Plus
+SoC, featuring a quad Cortex-A53, Cortex-M7 co-processor, 4GB LPDDR4,
+32GB eMMC, Wi-Fi 6/Bluetooth 5.4/802.15.4 tri-radio, Ethernet, HDMI/MIPI
+display interfaces, camera connectors, and standard expansion headers.
+
+Based on the device tree found in the NXP repository at github
+https://github.com/nxp-imx-support/meta-imx-frdm and on imx8mp-evk
+board kernel mainline device tree.
+
+This is a basic device tree supporting:
+
+ - Quad Cortex-A53
+ - 4GB LPDDR4 DRAM
+ - PCA9450C PMIC with regulators
+ - Two NXP PCAL6416 GPIO expanders
+ - RGB LEDs via GPIO expander
+ - I2C1, I2C2, I2C3 controllers
+ - UART2 (console) and UART3 (with RTS/CTS)
+ - USDHC3 (8-bit eMMC)
+ - SNVS power key (onboard power button)
+
+Co-developed-by: Xiaofeng Wei <xiaofeng.wei@nxp.com>
+Signed-off-by: Xiaofeng Wei <xiaofeng.wei@nxp.com>
+Signed-off-by: Rogerio Pimentel <rpimentel.silva@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm64/boot/dts/freescale/Makefile        |   1 +
+ arch/arm64/boot/dts/freescale/imx8mp-frdm.dts | 355 ++++++++++++++++++++++++++
+ 2 files changed, 356 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
+
+diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
+index 525ef180481d..d861e576779a 100644
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -206,6 +206,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
+ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb
+ dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb
+ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
++dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb
+ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb
+ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb
+ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
+new file mode 100644
+index 000000000000..55690f5e53d7
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
+@@ -0,0 +1,355 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright 2019 NXP
++ */
++
++/dts-v1/;
++
++#include "imx8mp.dtsi"
++
++/ {
++	model = "NXP i.MX8MPlus FRDM board";
++	compatible = "fsl,imx8mp-frdm", "fsl,imx8mp";
++
++	chosen {
++		stdout-path = &uart2;
++	};
++
++	gpio-leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			label = "red";
++			gpios = <&pcal6416_0 13 GPIO_ACTIVE_HIGH>;
++			default-state = "off";
++		};
++
++		led-1 {
++			label = "green";
++			gpios = <&pcal6416_0 14 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++
++		led-2 {
++			label = "blue";
++			gpios = <&pcal6416_0 15 GPIO_ACTIVE_HIGH>;
++			default-state = "off";
++		};
++	};
++
++	memory@40000000 {
++		device_type = "memory";
++		reg = <0x0 0x40000000 0 0xc0000000>,
++		      <0x1 0x00000000 0 0x40000000>;
++	};
++};
++
++&A53_0 {
++	cpu-supply = <&reg_arm>;
++};
++
++&A53_1 {
++	cpu-supply = <&reg_arm>;
++};
++
++&A53_2 {
++	cpu-supply = <&reg_arm>;
++};
++
++&A53_3 {
++	cpu-supply = <&reg_arm>;
++};
++
++&i2c1 {
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_i2c1>;
++	status = "okay";
++
++	pmic@25 {
++		compatible = "nxp,pca9450c";
++		reg = <0x25>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pinctrl_pmic>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
++
++		regulators {
++			BUCK1 {
++				regulator-name = "BUCK1";
++				regulator-min-microvolt = <720000>;
++				regulator-max-microvolt = <1000000>;
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-ramp-delay = <3125>;
++			};
++
++			reg_arm: BUCK2 {
++				regulator-name = "BUCK2";
++				regulator-min-microvolt = <720000>;
++				regulator-max-microvolt = <1025000>;
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-ramp-delay = <3125>;
++				nxp,dvs-run-voltage = <950000>;
++				nxp,dvs-standby-voltage = <850000>;
++			};
++
++			BUCK4 {
++				regulator-name = "BUCK4";
++				regulator-min-microvolt = <3000000>;
++				regulator-max-microvolt = <3600000>;
++				regulator-boot-on;
++				regulator-always-on;
++			};
++
++			reg_buck5: BUCK5 {
++				regulator-name = "BUCK5";
++				regulator-min-microvolt = <1650000>;
++				regulator-max-microvolt = <1950000>;
++				regulator-boot-on;
++				regulator-always-on;
++			};
++
++			BUCK6 {
++				regulator-name = "BUCK6";
++				regulator-min-microvolt = <1045000>;
++				regulator-max-microvolt = <1155000>;
++				regulator-boot-on;
++				regulator-always-on;
++			};
++
++			LDO1 {
++				regulator-name = "LDO1";
++				regulator-min-microvolt = <1650000>;
++				regulator-max-microvolt = <1950000>;
++				regulator-boot-on;
++				regulator-always-on;
++			};
++
++			LDO3 {
++				regulator-name = "LDO3";
++				regulator-min-microvolt = <1710000>;
++				regulator-max-microvolt = <1890000>;
++				regulator-boot-on;
++				regulator-always-on;
++			};
++
++			LDO5 {
++				regulator-name = "LDO5";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-boot-on;
++				regulator-always-on;
++			};
++		};
++	};
++
++	pcal6416_0: gpio@20 {
++		compatible = "nxp,pcal6416";
++		reg = <0x20>;
++		gpio-controller;
++		#gpio-cells = <2>;
++		interrupt-controller;
++		#interrupt-cells = <2>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pinctrl_pcal6416_0_int>;
++		interrupt-parent = <&gpio3>;
++		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
++		gpio-line-names = "CSI1_nRST",
++			"CSI2_nRST",
++			"DSI_CTP_RST",
++			"EXT_PWREN1",
++			"CAN_STBY",
++			"EXP_P0_5",
++			"EXP_P0_6",
++			"P0_7",
++			"LVDS0_BLT_EN",
++			"LVDS1_BLT_EN",
++			"LVDS0_CTP_RST",
++			"LVDS1_CTP_RST",
++			"SPK_PWREN",
++			"RLED_GPIO",
++			"GLED_GPIO",
++			"BLED_GPIO";
++	};
++
++	pcal6416_1: gpio@21 {
++		compatible = "nxp,pcal6416";
++		reg = <0x21>;
++		gpio-controller;
++		#gpio-cells = <2>;
++		interrupt-controller;
++		#interrupt-cells = <2>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pinctrl_pcal6416_1_int>;
++		interrupt-parent = <&gpio2>;
++		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++		gpio-line-names = "P0_0",
++			"P0_1",
++			"AUD_nINT",
++			"RTC_nINTA",
++			"USB1_SS_SEL",
++			"USB2_PWR_EN",
++			"SPI_EXP_SEL",
++			"P0_7",
++			"W2_HOST_WAKE_SD_3V3",
++			"W2_HOST_WAKE_BT_3V3",
++			"EXP_WIFI_BT_PDN_3V3",
++			"EXP_BT_RST_3V3",
++			"W2_RST_IND_3V3",
++			"SPI_nINT_3V3",
++			"KEYM_PCIE_nWAKE",
++			"P1_7";
++	};
++};
++
++&i2c2 {
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_i2c2>;
++	status = "okay";
++};
++
++&i2c3 {
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_i2c3>;
++	status = "okay";
++};
++
++&snvs_pwrkey {
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_uart2>;
++	status = "okay";
++};
++
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_uart3>;
++	assigned-clocks = <&clk IMX8MP_CLK_UART3>;
++	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
++	uart-has-rtscts;
++	status = "okay";
++};
++
++&usdhc3 {
++	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
++	assigned-clock-rates = <400000000>;
++	pinctrl-names = "default", "state_100mhz", "state_200mhz";
++	pinctrl-0 = <&pinctrl_usdhc3>;
++	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
++	bus-width = <8>;
++	non-removable;
++	status = "okay";
++};
++
++&iomuxc {
++	pinctrl_i2c1: i2c1grp {
++		fsl,pins = <
++			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL	0x400001c2
++			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA	0x400001c2
++		>;
++	};
++
++	pinctrl_i2c2: i2c2grp {
++		fsl,pins = <
++			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL	0x400001c2
++			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA	0x400001c2
++		>;
++	};
++
++	pinctrl_i2c3: i2c3grp {
++		fsl,pins = <
++			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL	0x400001c2
++			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA	0x400001c2
++		>;
++	};
++
++	pinctrl_pmic: pmicgrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x000001c0
++		>;
++	};
++
++	pinctrl_pcal6416_0_int: pcal6416-0-int-grp {
++		fsl,pins = <
++			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x146
++		>;
++	};
++
++	pinctrl_pcal6416_1_int: pcal6416-1-int-grp {
++		fsl,pins = <
++			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11	0x146
++		>;
++	};
++
++	pinctrl_uart2: uart2grp {
++		fsl,pins = <
++			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
++			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
++		>;
++	};
++
++	pinctrl_uart3: uart3grp {
++		fsl,pins = <
++			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX	0x140
++			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX	0x140
++			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS	0x140
++			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS	0x140
++		>;
++	};
++
++	pinctrl_usdhc3: usdhc3grp {
++		fsl,pins = <
++			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
++			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
++			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
++			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
++			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
++			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
++			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
++			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
++			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
++			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
++			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
++		>;
++	};
++
++	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
++			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
++			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
++			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
++			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
++			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
++			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
++			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
++			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
++			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
++			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
++		>;
++	};
++
++	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
++			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
++			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
++			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
++			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
++			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
++			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
++			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
++			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
++			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
++			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
++		>;
++	};
++};
diff --git a/configs/platform-v8a/patches/linux-6.18/0002-dts-imx8mp-frdm-import-downstream-changes.patch b/configs/platform-v8a/patches/linux-6.18/0002-dts-imx8mp-frdm-import-downstream-changes.patch
new file mode 100644
index 0000000000000000000000000000000000000000..cb8b67381b7f662f8c2dc97812673390b9c78400
--- /dev/null
+++ b/configs/platform-v8a/patches/linux-6.18/0002-dts-imx8mp-frdm-import-downstream-changes.patch
@@ -0,0 +1,580 @@
+From: Fabian Pfitzner <f.pfitzner@pengutronix.de>
+Date: Wed, 7 Jan 2026 16:58:37 +0100
+Subject: [PATCH] dts: imx8mp-frdm: import downstream changes
+
+Import NXP downstream dts [1].
+These changes integrate support for
+
+- SD Card
+- Ethernet (FEC + EQOS)
+- USB
+- Wifi
+- HDMI
+
+[1] https://github.com/nxp-imx/linux-imx
+
+Signed-off-by: Fabian Pfitzner <f.pfitzner@pengutronix.de>
+---
+ arch/arm64/boot/dts/freescale/imx8mp-frdm.dts | 499 ++++++++++++++++++++++++++
+ 1 file changed, 499 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
+index 55690f5e53d7..d7e054282670 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts
+@@ -5,6 +5,7 @@
+ 
+ /dts-v1/;
+ 
++#include <dt-bindings/usb/pd.h>
+ #include "imx8mp.dtsi"
+ 
+ / {
+@@ -42,6 +43,81 @@ memory@40000000 {
+ 		reg = <0x0 0x40000000 0 0xc0000000>,
+ 		      <0x1 0x00000000 0 0x40000000>;
+ 	};
++
++	native-hdmi-connector {
++		compatible = "hdmi-connector";
++		label = "HDMI OUT";
++		type = "a";
++
++		port {
++			hdmi_in: endpoint {
++				remote-endpoint = <&hdmi_tx_out>;
++			};
++		};
++	};
++
++	usdhc1_pwrseq: usdhc1_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
++	};
++
++	reg_usdhc1_vmmc: regulator-usdhc1 {
++		compatible = "regulator-fixed";
++		regulator-name = "WLAN_EN";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		gpio = <&pcal6416_1 10 GPIO_ACTIVE_HIGH>;
++		/*
++		 * IW612 wifi chip needs more delay than other wifi chips to complete
++		 * the host interface initialization after power up, otherwise the
++		 * internal state of IW612 may be unstable, resulting in the failure of
++		 * the SDIO3.0 switch voltage.
++		 */
++		startup-delay-us = <20000>;
++		enable-active-high;
++	};
++
++	reg_usdhc2_vmmc: regulator-usdhc2 {
++		compatible = "regulator-fixed";
++		pinctrl-names = "default";
++		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
++		regulator-name = "VSD_3V3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++	};
++
++	reg_usb_vbus: regulator-vbus {
++		compatible = "regulator-fixed";
++		pinctrl-names = "default";
++		regulator-name = "USB_VBUS";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pcal6416_1 5 GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++		regulator-always-on;
++	};
++
++	reg_vext_3v3: regulator-vext-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "VEXT_3V3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	cbtl04gp {
++		compatible = "nxp,cbtl04gp";
++		pinctrl-names = "default";
++		switch-gpios = <&pcal6416_1 4 GPIO_ACTIVE_LOW>;
++		orientation-switch;
++
++		port {
++			usb3_data_ss: endpoint {
++				remote-endpoint = <&typec_con_ss>;
++			};
++		};
++	};
+ };
+ 
+ &A53_0 {
+@@ -60,6 +136,33 @@ &A53_3 {
+ 	cpu-supply = <&reg_arm>;
+ };
+ 
++&lcdif3 {
++	status = "okay";
++};
++
++
++&hdmi_pvi {
++	status = "okay";
++};
++
++&hdmi_tx {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_hdmi>;
++	status = "okay";
++
++	ports {
++		port@1 {
++			hdmi_tx_out: endpoint {
++				remote-endpoint = <&hdmi_in>;
++			};
++		};
++	};
++};
++
++&hdmi_tx_phy {
++	status = "okay";
++};
++
+ &i2c1 {
+ 	clock-frequency = <400000>;
+ 	pinctrl-names = "default";
+@@ -202,6 +305,46 @@ pcal6416_1: gpio@21 {
+ 			"KEYM_PCIE_nWAKE",
+ 			"P1_7";
+ 	};
++
++	ptn5110: tcpc@50 {
++		compatible = "nxp,ptn5110";
++		pinctrl-names = "default";
++		reg = <0x50>;
++		pinctrl-0 = <&pinctrl_typec>;
++		interrupt-parent = <&gpio4>;
++		interrupts = <19 8>;
++
++		port {
++			typec_dr_sw: endpoint {
++				remote-endpoint = <&usb3_drd_sw>;
++			};
++		};
++
++		usb_con: connector {
++			compatible = "usb-c-connector";
++			label = "USB-C";
++			power-role = "dual";
++			data-role = "dual";
++			try-power-role = "sink";
++			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
++			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
++					 PDO_VAR(5000, 20000, 3000)>;
++			op-sink-microwatt = <15000000>;
++			self-powered;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				port@1 {
++					reg = <1>;
++					typec_con_ss: endpoint {
++						remote-endpoint = <&usb3_data_ss>;
++					};
++				};
++			};
++		};
++	};
+ };
+ 
+ &i2c2 {
+@@ -218,6 +361,54 @@ &i2c3 {
+ 	status = "okay";
+ };
+ 
++&usb3_phy0 {
++	fsl,phy-tx-vref-tune-percent = <122>;
++	fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
++	fsl,phy-tx-vboost-level-microvolt = <1156>;
++	fsl,phy-comp-dis-tune-percent = <115>;
++	fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>;
++	fsl,phy-pcs-tx-swing-full-percent = <100>;
++	status = "okay";
++};
++
++&usb3_0 {
++	status = "okay";
++};
++
++&usb_dwc3_0 {
++	dr_mode = "otg";
++	hnp-disable;
++	srp-disable;
++	adp-disable;
++	usb-role-switch;
++	role-switch-default-mode = "none";
++	snps,dis-u1-entry-quirk;
++	snps,dis-u2-entry-quirk;
++	status = "okay";
++
++	port {
++		usb3_drd_sw: endpoint {
++			remote-endpoint = <&typec_dr_sw>;
++		};
++	};
++};
++
++&usb3_phy1 {
++	fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
++	fsl,phy-tx-vref-tune-percent = <116>;
++	status = "okay";
++};
++
++&usb3_1 {
++	status = "okay";
++};
++
++&usb_dwc3_1 {
++	vbus-supply = <&reg_usb_vbus>;
++	dr_mode = "host";
++	status = "okay";
++};
++
+ &snvs_pwrkey {
+ 	status = "okay";
+ };
+@@ -237,6 +428,40 @@ &uart3 {
+ 	status = "okay";
+ };
+ 
++&usdhc1 {
++	pinctrl-names = "default", "state_100mhz", "state_200mhz";
++	pinctrl-0 = <&pinctrl_usdhc1>;
++	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
++	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
++	mmc-pwrseq = <&usdhc1_pwrseq>;
++	vmmc-supply = <&reg_usdhc1_vmmc>;
++	bus-width = <4>;
++	keep-power-in-suspend;
++	non-removable;
++	wakeup-source;
++	status = "okay";
++
++	wifi_wake_host {
++		compatible = "nxp,wifi-wake-host";
++		interrupt-parent = <&gpio2>;
++		interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-names = "host-wake";
++	};
++};
++
++&usdhc2 {
++	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
++	assigned-clock-rates = <400000000>;
++	pinctrl-names = "default", "state_100mhz", "state_200mhz";
++	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
++	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
++	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
++	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
++	vmmc-supply = <&reg_usdhc2_vmmc>;
++	bus-width = <4>;
++	status = "okay";
++};
++
+ &usdhc3 {
+ 	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ 	assigned-clock-rates = <400000000>;
+@@ -249,7 +474,193 @@ &usdhc3 {
+ 	status = "okay";
+ };
+ 
++&eqos {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_eqos>;
++	phy-mode = "rgmii-id";
++	phy-handle = <&ethphy0>;
++	snps,force_thresh_dma_mode;
++	snps,mtl-tx-config = <&mtl_tx_setup>;
++	snps,mtl-rx-config = <&mtl_rx_setup>;
++	status = "okay";
++
++	mdio {
++		compatible = "snps,dwmac-mdio";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		ethphy0: ethernet-phy@2 {
++			compatible = "ethernet-phy-ieee802.3-c22";
++			reg = <2>;
++			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
++			reset-assert-us = <10000>;
++			reset-deassert-us = <80000>;
++			realtek,clkout-disable;
++		};
++	};
++
++	mtl_tx_setup: tx-queues-config {
++		snps,tx-queues-to-use = <5>;
++		snps,tx-sched-sp;
++
++		queue0 {
++			snps,dcb-algorithm;
++			snps,priority = <0x1>;
++		};
++
++		queue1 {
++			snps,dcb-algorithm;
++			snps,priority = <0x2>;
++		};
++
++		queue2 {
++			snps,dcb-algorithm;
++			snps,priority = <0x4>;
++		};
++
++		queue3 {
++			snps,dcb-algorithm;
++			snps,priority = <0x8>;
++		};
++
++		queue4 {
++			snps,dcb-algorithm;
++			snps,priority = <0xf0>;
++		};
++	};
++
++	mtl_rx_setup: rx-queues-config {
++		snps,rx-queues-to-use = <5>;
++		snps,rx-sched-sp;
++
++		queue0 {
++			snps,dcb-algorithm;
++			snps,priority = <0x1>;
++			snps,map-to-dma-channel = <0>;
++		};
++
++		queue1 {
++			snps,dcb-algorithm;
++			snps,priority = <0x2>;
++			snps,map-to-dma-channel = <1>;
++		};
++
++		queue2 {
++			snps,dcb-algorithm;
++			snps,priority = <0x4>;
++			snps,map-to-dma-channel = <2>;
++		};
++
++		queue3 {
++			snps,dcb-algorithm;
++			snps,priority = <0x8>;
++			snps,map-to-dma-channel = <3>;
++		};
++
++		queue4 {
++			snps,dcb-algorithm;
++			snps,priority = <0xf0>;
++			snps,map-to-dma-channel = <4>;
++		};
++	};
++};
++
++&fec {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_fec>;
++	phy-mode = "rgmii-id";
++	phy-handle = <&ethphy1>;
++	fsl,magic-packet;
++	status = "okay";
++
++	mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		ethphy1: ethernet-phy@1 {
++			compatible = "ethernet-phy-ieee802.3-c22";
++			reg = <1>;
++			eee-broken-1000t;
++			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
++			reset-assert-us = <10000>;
++			reset-deassert-us = <80000>;
++			realtek,aldps-enable;
++			realtek,clkout-disable;
++		};
++	};
++};
++
+ &iomuxc {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_hog>;
++
++	pinctrl_eqos: eqosgrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
++			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
++			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90
++			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90
++			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90
++			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90
++			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
++			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90
++			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16
++			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16
++			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16
++			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16
++			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
++			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
++			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x10
++		>;
++	};
++
++	pinctrl_fec: fecgrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x2
++			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x2
++			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90
++			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90
++			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90
++			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90
++			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90
++			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90
++			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16
++			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16
++			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16
++			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16
++			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16
++			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16
++			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x10
++		>;
++	};
++
++	pinctrl_hdmi: hdmigrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x1c2
++			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x1c2
++			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x10
++		>;
++	};
++
++	pinctrl_i2c1: i2c1grp {
++		fsl,pins = <
++			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2
++			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2
++		>;
++	};
++
++	pinctrl_typec: typec1grp {
++		fsl,pins = <
++			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x1c4
++		>;
++	};
++
++	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
++		>;
++	};
++
+ 	pinctrl_i2c1: i2c1grp {
+ 		fsl,pins = <
+ 			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL	0x400001c2
+@@ -305,6 +716,94 @@ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS	0x140
+ 		>;
+ 	};
+ 
++	pinctrl_usdhc1: usdhc1grp {
++		fsl,pins = <
++			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
++			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
++			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
++			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
++			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
++			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
++		>;
++	};
++
++	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
++			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
++			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4
++			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4
++			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4
++			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4
++		>;
++	};
++
++	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
++			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
++			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
++			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
++			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
++			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
++		>;
++	};
++
++	pinctrl_hog: hoggrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x40000010
++		>;
++	};
++
++	pinctrl_uart2: uart2grp {
++		fsl,pins = <
++			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
++			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
++		>;
++	};
++
++	pinctrl_usdhc2: usdhc2grp {
++		fsl,pins = <
++			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
++			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
++			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
++			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
++			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
++			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
++			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
++		>;
++	};
++
++	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
++			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
++			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
++			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
++			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
++			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
++			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
++		>;
++	};
++
++	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
++			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
++			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
++			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
++			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
++			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
++			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
++		>;
++	};
++
++	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
++		>;
++	};
++
+ 	pinctrl_usdhc3: usdhc3grp {
+ 		fsl,pins = <
+ 			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
diff --git a/configs/platform-v8a/patches/linux-6.18/series b/configs/platform-v8a/patches/linux-6.18/series
new file mode 100644
index 0000000000000000000000000000000000000000..1330df3ce9705634a752d799e602263edee31be1
--- /dev/null
+++ b/configs/platform-v8a/patches/linux-6.18/series
@@ -0,0 +1,5 @@
+# generated by git-ptx-patches
+#tag:base --start-number 1
+0001-arm64-dts-add-support-for-NXP-i.MX8MP-FRDM-board.patch
+0002-dts-imx8mp-frdm-import-downstream-changes.patch
+# 6f01bc63173b98edaf699be9b07d4caa  - git-ptx-patches magic

-- 
2.47.3

[DistroKit] [PATCH 6/6] doc: add imx8mp-frdm

[Fabian Pfitzner]

---
 doc/hardware_v8a_imx8mp_frdm.rst | 46 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/doc/hardware_v8a_imx8mp_frdm.rst b/doc/hardware_v8a_imx8mp_frdm.rst
new file mode 100644
index 0000000000000000000000000000000000000000..bb2bad7f6cddf0bc525fecc3abac74cd486fbaa9
--- /dev/null
+++ b/doc/hardware_v8a_imx8mp_frdm.rst
@@ -0,0 +1,46 @@
+NXP i.MX8MP FRDM Development Board
+=================================
+
+
+Boot Media
+----------
+
+Booting is available via multiple sources (Compare Table 3: Boot Switch Configuration in Quick Start Guide)
+
+.. csv-table:: Boot Switch :rst:dir:`csv-table`
+   :header: "Boot Mode", "SW5-1", "SW5-2", "SW5-3", "SW5-4"
+
+   "Boot from Internal Fuses",      "0", "0", "0", "0"
+   "Serial Downloader",             "0", "0", "0", "1"
+   "Boot from USDHC3 eMMC 5.1",     "0", "0", "1", "0"
+   "Boot from USDHC2 SD card",      "0", "0", "1", "1"
+
+
+Booting from USB and NFS
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Upload the bootloader ``platform-v8a/images/barebox-nxp-imx8mp-frdm.img`` via USB:
+
+.. code-block:: shell
+
+    platform-v8a/sysroot-host/bin/imx-usb-loader platform-v8a/images/barebox-nxp-imx8mp-frdm.img
+
+In Barebox, set the default boot location to nfs:
+
+    nv boot.default nfs://dude05//ptx/work/user/fpf/DistroKit/platform-v8a/root
+
+replace the path to one, where you have compiled your Distrokit
+
+
+Booting via SD-Card
+~~~~~~~~~~~~~~~~~~~
+
+Write the image ``platform-v8a/images/imx8mp-frdm.img`` to a microSD card. Put the
+microSD card into the board and boot it.
+
+
+Serial Console
+--------------
+
+The serial boot console is available via the USB-C Debug connector on the board.
+It brings 2 UARTS, whereas the first is the serial console used by kernel and bootloader.

-- 
2.47.3

Re: [DistroKit] [PATCH 1/6] v8a: add imx8mp-frdm image

[Michael Olbrich]

On Tue, Jan 20, 2026 at 05:42:34PM +0100, Fabian Pfitzner wrote:
> Signed-off-by: Fabian Pfitzner <f.pfitzner@pengutronix.de>
> ---
>  .../platform-v8a/platforms/image-imx8mp-frdm.in    | 10 +++++++
>  configs/platform-v8a/rules/image-imx8mp-frdm.make  | 35 ++++++++++++++++++++++
>  2 files changed, 45 insertions(+)
> 
> diff --git a/configs/platform-v8a/platforms/image-imx8mp-frdm.in b/configs/platform-v8a/platforms/image-imx8mp-frdm.in
> new file mode 100644
> index 0000000000000000000000000000000000000000..851eebee55c1769f4fcc08ac7d8348c09263484f
> --- /dev/null
> +++ b/configs/platform-v8a/platforms/image-imx8mp-frdm.in
> @@ -0,0 +1,10 @@
> +## SECTION=image
> +
> +config IMAGE_IMX8MP_FRDM
> +	tristate
> +	select HOST_GENIMAGE
> +	select IMAGE_ROOT_EXT
> +	select BAREBOX
> +	prompt "Generate images/imx8mp-frdm.img"
> +	help
> +	  Generate a bootable SD card image to deploy a NXP i.MX8MP-FRDM board.
> diff --git a/configs/platform-v8a/rules/image-imx8mp-frdm.make b/configs/platform-v8a/rules/image-imx8mp-frdm.make
> new file mode 100644
> index 0000000000000000000000000000000000000000..e602d59eae68b67f36c78e22a67059a7df3b252b
> --- /dev/null
> +++ b/configs/platform-v8a/rules/image-imx8mp-frdm.make
> @@ -0,0 +1,35 @@
> +# -*-makefile-*-
> +#
> +# Copyright (C) 2025 by Fabian Pfitzner <f.pfitzner@pengutronix.de>
> +#
> +# For further information about the PTXdist project and license conditions
> +# see the README file.
> +#
> +
> +#
> +# We provide this package
> +#
> +IMAGE_PACKAGES-$(PTXCONF_IMAGE_IMX8MP_FRDM) += image-imx8mp-frdm
> +
> +#
> +# Paths and names
> +#
> +IMAGE_IMX8MP_FRDM		:= image-imx8mp-fdrm
> +IMAGE_IMX8MP_FRDM_DIR	:= $(BUILDDIR)/$(IMAGE_IMX8MP_FRDM)
> +IMAGE_IMX8MP_FRDM_IMAGE	:= $(IMAGEDIR)/imx8mp-frdm.img
> +IMAGE_IMX8MP_FRDM_FILES	:= $(IMAGEDIR)/root.tgz
> +IMAGE_IMX8MP_FRDM_CONFIG	:= imx8m.config

The indention looks wrong. The ':=' should be aligned.

Michael


> +
> +# ----------------------------------------------------------------------------
> +# Image
> +# ----------------------------------------------------------------------------
> +
> +IMAGE_IMX8MP_FRDM_ENV := \
> +        BAREBOX_IMAGE=barebox-nxp-imx8mp-frdm.img
> +
> +$(IMAGE_IMX8MP_FRDM_IMAGE):
> +	@$(call targetinfo)
> +	@$(call image/genimage, IMAGE_IMX8MP_FRDM)
> +	@$(call finish)
> +
> +# vim: syntax=make
> 
> -- 
> 2.47.3
> 
> 
> 

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